The total current in the opamp, $\mathrm{I}_{\text {total }}$, excluding the current in the bias network, is equal to $\mathrm{I}_{\mathrm{D} 3}+\mathrm{I}_{\mathrm{D} 4}$, which is equal to $2\left(I_{D 1}+I_{D 6}\right)$. Defining $I_B \equiv I_{D 5}=I_{D 6}$ and noting that we are asked to make $I_{D 1}=4 I_{D 6}$, we have

$$
\mathrm{I}_{\text {total }}=2\left(\mathrm{I}_{\mathrm{D} 1}+\mathrm{I}_{\mathrm{D} 6}\right)=2\left(4 \mathrm{I}_{\mathrm{B}}+\mathrm{I}_{\mathrm{B}}\right)=10 \mathrm{I}_{\mathrm{B}}
$$


Since the current dissipation is specified to be 0.4 mA , we have

$$
\mathrm{I}_{\mathrm{B}}=\mathrm{I}_{\mathrm{D} 5}=\mathrm{I}_{\mathrm{D} 6}=\frac{\mathrm{I}_{\text {total }}}{10}=40 \mu \mathrm{~A}
$$


This bias current for $I_B$ implies that $I_{D 3}=I_{D 4}=5 I_{D 5}=200 \mu \mathrm{~A}$, and $I_{D 1}=I_{D 2}=4 I_{D 5}=160 \mu \mathrm{~A}$. Now, we let all transistor channel lengths be $0.4 \mu \mathrm{~m}$, about $2 \times$ larger than the minimum gate length in this technology. This choice allows us to immediately determine the sizes of most transistors using

$$
\left(\frac{W}{L}\right)_i=\frac{2 I_{D i}}{\mu_i C_{o x} V_{e f f i}^2}
$$

and then round to the closest multiple of $2 \mu \mathrm{~m}$ in transistor widths. Input transis ors $\mathrm{Q}_1$ and $\mathrm{Q}_2$ were an exception; their widths are set at the prescribed maximum of $180 \mu \mathrm{~m}$. This puts those devices on the border of subthreshold operation, thereby maximizing their transconductance for the given bias current. Table 6.1 lists reasonable values for the resulting dimensions of all transistors. Note that the larger widths are exactly divisible by the smaller widths of a transistor of the same type and thus allows larger transistors to be realized as a parallel combination of smaller transistors. The width of $Q_{11}$ was determined from the requirement that $I_{D 11}=I_{D 3} / 10=20 \mu \mathrm{~A}=I_{\text {bias, } 1}$. The widths of $Q_{12}$ and $Q_{13}$ were somewhat arbitrarily chosen to equal the width of $\mathrm{Q}_{11}$.

Under a square-law assumption, the transconductance of the input transistors would be given by

$$
\sqrt{2 \mathrm{I}_{\mathrm{D} 1} \mu_{\mathrm{n}} \mathrm{C}_{\mathrm{ox}}(\mathrm{~W} / \mathrm{L})_1}=6.24 \mathrm{~mA} / \mathrm{V}
$$


However, this is greater than the maximum transconductance achieved in subthreshold operation.

$$
\mathrm{g}_{\mathrm{m} 1(\mathrm{sub}-\mathrm{th})}=\frac{\mathrm{ql}_{\mathrm{D} 1}}{\mathrm{nkT}}=4 \mathrm{~mA} / \mathrm{V}
$$


The maximum value computed in (6.110) is assumed as an approximation, although the real transconductance will be less than this upper limit. The unity-gain frequency of the opamp is given by

$$
\omega_{\mathrm{ta}}=\frac{\mathrm{g}_{\mathrm{ml}}}{\mathrm{C}_{\mathrm{L}}}=1.6 \times 10^9 \mathrm{rad} / \mathrm{s} \Rightarrow \mathrm{f}_{\mathrm{ta}}=255 \mathrm{MHz}
$$

The slew rate without the clamp transistors is given by

$$
\mathrm{SR}=\frac{\mathrm{I}_{\mathrm{D} 4}}{\mathrm{C}_{\mathrm{L}}}=80 \mathrm{~V} / \mu \mathrm{s}
$$


When the clamp transistors are included, during slew-rate limiting, we have

$$
\mathrm{I}_{\mathrm{D} 12}+\mathrm{I}_{\mathrm{D} 3}=\mathrm{I}_{\mathrm{bias} 2}
$$


But

$$
\mathrm{I}_{\mathrm{D} 3}=10 \mathrm{I}_{\mathrm{D} 11}
$$

and

$$
\mathrm{I}_{\mathrm{D} 11}=20 \mu \mathrm{~A}+\mathrm{I}_{\mathrm{D} 12}
$$


Substituting (6.114) and (6.115) into (6.113) and solving for $\mathrm{I}_{\mathrm{D} 11}$ gives

$$
I_{D 11}=\frac{I_{\text {bias } 2}+20 \mu \mathrm{~A}}{11}
$$

which implies that the value of $\mathrm{I}_{\mathrm{D} 11}$ during slew-rate limiting is $30.9 \mu \mathrm{~A}$ and $\mathrm{I}_{\mathrm{D} 3}=\mathrm{I}_{\mathrm{D} 4}=10 \mathrm{I}_{\mathrm{D} 11}=0.309 \mathrm{~mA}$, which is substantially larger than the slew current available without the clamp transistors. This larger bias current will give a slew-rate value of

$$
\mathrm{SR}=\frac{\mathrm{I}_{\mathrm{D} 4}}{\mathrm{C}_{\mathrm{L}}}=124 \mathrm{~V} / \mu \mathrm{s}
$$

More importantly, the time it takes to recover from slew-rate limiting will be substantially decreased.